Dynamic random access memory (DRAM) devices have traditionally employed a substrate bias voltage on the N-channel transistors to improve latch up immunity, cell isolation, and circuit speed. However, for submicron devices, the substrate bias enhances an undesirable short channel effect. This short channel effect produces a large threshold voltage difference between devices of different sizes when the substrate bias voltage is applied. Such a large difference between devices of different sizes make the control of the threshold voltage very difficult.
Attempts to overcome this short channel effect problem include using triple well isolation to allow for different substrate biases to be applied to different parts of the dynamic random access memory. However, the triple well approach uses an unconventional n- type substrate and isolation with various p- type wells. Further, the depth of the p- type wells limit the depth for a trench in the memory array of the DRAM device. Since the trench wall is doped with an N+ conductivity type, any contact of the trench with the n- type substrate will short the trenches together. Therefore, it is desirable to overcome the short channel effect and trench depth problems through a more conventional process.